SK Hynix crossed a $1 trillion market cap on AI memory demand. HBM, not GPUs, is the actual constraint on inference capacity. What developers need to know about hardware economics.
SK Hynix crossed $1 trillion in market capitalization on June 3, 2026 — the first time a memory chip company has reached that threshold. TSMC did it on GPU fabrication demand. Nvidia did it on GPU design. SK Hynix did it on memory. The market is telling you something specific: the constraint in the AI supply chain has shifted from compute to memory bandwidth.
This matters for developers because it is the root cause behind inference pricing trends, the reason H100 cluster availability is still constrained despite TSMC ramping H200 production, and the bottleneck that HBM4 is designed to address. Understanding the hardware economics is not academic — it directly affects what models you can afford to run and when costs will fall.
What Is HBM and Why Does It Matter
High Bandwidth Memory is the type of DRAM stacked directly on a GPU or AI accelerator die using 3D packaging technology. It is not regular DDR5 RAM. HBM sits inside the same package as the compute die, connected via silicon interposer with thousands of parallel data paths — versus the handful of lanes that connect a CPU to its DRAM slots.
The bandwidth difference is extreme:
| Memory type | Bandwidth | Used in |
|---|---|---|
| DDR5 (standard server RAM) | ~90 GB/s per channel | CPUs, standard servers |
| GDDR6X | ~960 GB/s | Consumer GPUs (RTX 4090) |
| HBM2e | ~3.2 TB/s | A100 GPU |
| HBM3 | ~3.9 TB/s | H100 GPU |
| HBM3e | ~4.8 TB/s | H200, MI300X |
| HBM4 (expected 2026–2027) | ~8–12 TB/s | Next-gen AI accelerators (B200+) |
Why bandwidth matters for AI inference: large language model inference is memory-bandwidth-bound, not compute-bound. For every token generated, the GPU must load the model weights from HBM to the compute cores. A 70-billion parameter model in float16 requires 140GB of storage and must be partially loaded for each forward pass. The speed at which weights move from HBM to compute cores determines tokens-per-second.
More FLOPs does not help when the bottleneck is weight loading speed. That is why Nvidia’s H200 — which uses HBM3e instead of H200’s HBM3 — achieves roughly 45% higher LLM throughput despite having identical compute cores. The GPU die did not change. The memory bandwidth doubled.
Why SK Hynix Is the Critical Dependency
HBM manufacturing requires a specific process: stacking multiple DRAM dies vertically and connecting them with thousands of through-silicon vias (TSVs). Only three companies in the world can manufacture HBM at production scale: SK Hynix, Samsung, and Micron.
Market share as of Q1 2026:
| Company | HBM market share | Primary customer |
|---|---|---|
| SK Hynix | ~52% | Nvidia (sole HBM3e supplier for H100/H200) |
| Samsung | ~30% | AMD, Google, internal |
| Micron | ~18% | Nvidia (qualified for H200 in late 2025) |
SK Hynix is the exclusive HBM3e supplier to Nvidia for H100 and H200 production. This is not a preference — it is the only company that passed Nvidia’s qualification testing at sufficient yield rates for HBM3e at the volume Nvidia requires. Micron was qualified for H200 in Q4 2025 but supplies only a fraction of total volume. Samsung has failed repeated Nvidia qualification tests for HBM3e through Q1 2026.
The result: Nvidia’s H100 and H200 production rate is bounded by SK Hynix’s HBM manufacturing capacity. Every time you hear “H100 supply is constrained,” you are hearing “SK Hynix is constrained.”
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